1. Field of the Invention
Embodiments of the present invention generally relate to a method and apparatus for depositing both a high k layer and a capping layer within the same processing chamber.
2. Description of the Related Art
In the field of semiconductor processing, flat-panel display processing or other electronic device processing, vapor deposition processes have played an important role in depositing materials on substrates. As the geometries of electronic devices continue to shrink and the density of devices continues to increase, the size and aspect ratio of the features are becoming more aggressive, e.g., feature sizes of 0.07 μm and aspect ratios of 10 or greater are being considered. Accordingly, conformal deposition of materials to form these devices is becoming increasingly important.
While conventional chemical vapor deposition (CVD) has proved successful for device geometries and aspect ratios down to 0.15 μm, the more aggressive device geometries require an alternative deposition technique. One technique that is receiving considerable attention is atomic layer deposition (ALD). During an ALD process, reactant gases are sequentially introduced into a process chamber containing a substrate. Generally, a first reactant is pulsed into the process chamber and is adsorbed onto the substrate surface. A second reactant is pulsed into the process chamber and reacts with the first reactant to form a deposited material. A purge step is typically carried out between the delivery of each reactant gas. The purge step may be a continuous purge with the carrier gas or a pulse purge between the delivery of the reactant gases.
The formation of high-k dielectric materials on complementary metal oxide semiconductor (CMOS) devices has been beneficial. However, when a metal containing electrode is utilized, the metal containing electrode may react with the high-k dielectric material and result in the threshold voltage (Vth) of the p-doped portion of the CMOS (PMOS) not matching the n-doped portion of the CMOS (NMOS). When the threshold voltages do not match, the CMOS device may not be efficient.
Therefore, there is a need in the art for a method and apparatus for making a CMOS structure utilizing both high-k dielectric material and metal containing electrodes.